Tentative course outline, CSC 258, Fall 2008

References below are as follows:

M&K

Mano & Kime, Logic and Computer Design Fundamentals, fourth edition, Prentice-Hall, 2008.
In some cases I've left in references to the second edition section numbers, when I have them around. 'e' stands for "edition"; "2e" is "second edition".

HVZ, or HVZ5e, or HVZxe for any x

Hamacher, Vranesic, and Zaky. 'e' stands for "edition", i.e. "5e" is "fifth edition". When I just write "HVZ", that means I think that maybe the section or chapter numbers will be the same in some earlier editions.

Course information (September 9)

• Course information sheet in HTML or PDF
• Also distributed many documents from the lab handouts directory: lab dates, lab notes, lab data sheets, practice lab.
• Also distributed
  • Boolean algebra operators and identities
  • Assignment one handout (for later)
• There is a document about textbooks.
• E-mail is the best way to reach me and to ask questions. You will get a CDF account on the basis of being enrolled in CSC 258 (or your "permanent" cdf account will be added to the 258 unix group, etc).
• Photo id student cards will be required during the midterm and the exam.
• Please find a lab partner.

Intro to logic gates, circuits, and boolean algebra (September 9)

• Levels of a computer system
• Intro gates etc in M&K 2-1 or HVZ A.1 (that's appendix A, section 1)
• Two different interpretations of boolean values:
  • 1) enable/disable: as in the light switch example, one state means to make something go, the other means to stop it. Also known as yes/no or true/false.
  • 2) numeric: one state means a zero, the other means a one.
  • Due to the influence of the numeric interpretation, we'll usually write the two states as 0 and 1, even when we're interested in the enable/disable/true/false interpretation. This should not be understood as a theoretical association of zero and one with true and false; nor does it mean that a zero is necessarily the state without current or a one the state with current.
• Boolean algebra topics: operators, precedence rules, laws
• More boolean algebra in M&K 2-2
• Boolean algebra operators and identities handout
• We proved the three absorption laws.

Combinational circuits (September 16 (and a bit of September 9))

• Characterization of combinational circuits (the following are alternative characterizations):
  • the outputs are a function (only) of the inputs.
  • the circuit is acyclic (no feedback from a gate to a "previous" gate, i.e. there exists a partial ordering of the set of gates such that the output of a gate is always connected only to "later" gates, with respect to this ordering).
  • the circuit is describable by a boolean expression.
• Adders: see M&K 4-2 (or 3-8 in 2e) or HVZ 5e section 6.1
• DNF/CNF, sum-of-products expressions, minimal sum-of-products expressions and Karnaugh maps
  • Mano&Kime 2-3, 2-4, and 2-5 (although I find that notation (which I think is a standard one) to be annoying)
  • HVZ A.2 and A.3
  • more thorough treatment in Langholz et al (see textbooks.html)
• basic combinational circuits (M&K 3-1)
• decoders (HVZ A.9; M&K 3-7 (or 3-5 in 2e)); seven-segment display decoder (HVZ A.9)
• multiplexers (HVZ A.10; M&K 3-9 (or 3-7 in 2e))
• PLAs (HVZ A.11.1; M&K 6-8)

Sequential circuits (September 23)

• SR latch (HVZ A.6 intro; M&K 5-2 (or 4-2 in 2e))
• D latch, clocked latches (HVZ A.6.1; M&K 5-2 (or 4-2 in 2e))
• what we want in a register (somewhat discussed in M&K 7-1 and 7-2 (or 6-1 and 6-2 in 2e))
• master-slave flip-flop (SR flip-flop, D flip-flop) (HVZ A.6.2 and some of A.6.3; M&K 5-3 (or 4-3 in 2e))
• JK flip-flop (HVZ A.6.5; M&K 5-3 (or 4-3 in 2e))
• counter (ripple counter) (HVZ A.8; M&K 7-6 (or 5-4 in 2e))
• synchronous counter (HVZ A.13.1 to some extent; M&K 7-6 (or 5-5 in 2e))
• register with parallel load, shift register, shift register with parallel load, etc (HVZ A.7; M&K 7-1 (or 5-2 in 2e))
• pictures shown in class

Computer arithmetic and two's-complement representation (September 30, approximately)

• more analytical examination of addition circuitry
• negative numbers and two's-complement representation
• overflow-bit computation
• some notes on multiplication

• Stallings chapter 8 or 9 (depending on edition) (see textbooks.html)
• M&K some of chapter 4 (or 3-8 through 3-11 in 2e)
• HVZ 5e chapter 6, especially 6.1 (it's also chapter 6 of 4e; but it's chapter 7 of 3e)
• HVZ section 2.1
• my notes for me (long and rambly -- basically, organized for talking rather than reading, but might be useful as a recap)

Memory organization (October 7)

• the machine language program resides in main memory;
  addresses;
  "byte-addressable", endian issues, use of octal/hexadecimal
  • the above are discussed in HVZ 2.2
• kinds of memory (RAM, ROM, PROM, EPROM, EEPROM) (HVZ section 5.1, and intro to section 5.2, and section 5.3)
• communication with the CPU (HVZ 2.3; M&K middle of 8-2 (or 6-2 in 2e))
• see notes re kinds of memory and communication.
  • We did the "kinds of memory" section fully.
  • We only briefly discussed the "communication between the CPU and the main memory unit" material, and we didn't introduce all of the terminology introduced in that section -- we'll revisit that part in detail when we talk about building a CPU, after machine language programming.

Machine-language programming (in general) (October 7 and 14)

• other registers in the CPU
• fetch/execute/store cycle
• kinds of machine-language instructions
• addressing modes; register transfer notation
• instruction formats (numbers of operands, etc)
• references are HVZ 2.4 through 2.6; or M&K chapter 10 and somewhat 9 (or chapter 6 in 2e)

Machine-language programming (October 14 and 21 and 28)

• example CPU and its basic characteristics
• addressing
• instructions
• subroutine linkage (the JSR and RTS instructions)

here went some odds and ends about the PDP-11 and branch instruction semantics and further multiword arithmetic details, and maybe floating-point numbers

CPU organization and microprogramming (October 28, November 4, 11)

• Simple one-bus architecture handout (PDF)
• Mano & Kime chapter 7 except for pipelining and verilog; and chapter 9 (except that my notation is better) (chapter 8 in 2e).
• Chapter 7 of HVZ 5e.
• some notes and pictures by me (summarizing major aspects of this material; mostly not tutorial in nature)
• "Tri-state device" discussion in HVZ 5e section A.5.4.
• My "tri-state device" notes are part of the above-cited web pages by me

Midterm, November 4, 6:00, NOT IN TUTORIAL ROOM

I/O (November 11)

• M&K chapter 12
• memory-mapped i/o (HVZ 5e chapter 4)
• notes and examples

Interrupts (November 11, 18)

• M&K 12-6 and 12-7 (or 11-6 and 11-7 in 2e).
• HVZ 5e section 4.2 and somewhat 4.3.
• HVZ 3e 6.3 and 6.4; HVZ 4e 4.2 and 4.3.
• my notes (still sketchy)

Some concepts in RISC CPU design (approximately November 18)

• M&K Chapter 11-3, and 11-1 and 11-2
• some basic concepts in HVZ 5e 8.1 or HVZ 4e 7.1
• instruction set design: M&K 11-3 or HVZ 5e 8.4 or HVZ 4e 7.5
• pipelining: M&K 11-1 and 11-2; HVZ 5e 8.1 through 8.3, 8.5; or HVZ 4e chapter 7
• basic three-bus architecture, HVZ 5e 8.5 or HVZ 4e 7.4
  • my pictures including the "operand forwarding" issue
• Caching is fairly important to RISC CPUs, and all other modern fast CPUs, but we won't have time to discuss it. I highly recommend reading some of chapter 13 of M&K (chapter 12 in 2e) (perhaps after the exam). Or there is discussion of caching in HVZ 5e 5.5 and 5.6, and then 8.1 again.
• register windows
• I've also posted some of my notes about RISC CPUs.

Gate construction (approximately November 25)

• Electronic realization of logic gates
• Some possible references for further information (see textbooks.html):
  • HVZ A.5 intro and A.5.1
  • Fortney for a solid reference for gate construction
  • Mano, Digital Design, for a gentler introduction to gate construction
• Some pictures

Physical limits affecting computer design; alternative architectures (December 2)

Review (December 2)