Assignment four sample solutions

These are just sample solutions! There are other possible valid answers.

Question 1

3. AddressFieldOfIR_out, MAR_in, Read, Wait MFC
4. MDR_out, Y_in
5. R0_out, Complement B, Set Carry-In, Add, Z_in, Set CC
6. Z_out, MDR_in, Write, Wait MFC, End

Question 2

2a

3. AddressFieldOfIR_out, MAR_in, Read, Wait MFC
4. MDR_out, R0_in, End

2b

3. AddressFieldOfIR_out, MAR_in
4. R0_out, MDR_in, Write, Wait MFC, End

2c

3. AddressFieldOfIR_out, MAR_in
4. R0_out, MDR_in, Read, Write, Wait MFC
5. MDR_out, R0_in, End

2d

a) read in cycle 3 is over by cycle 5, so it takes 6 cycles

b) write in cycle 4 is over by cycle 7, so it takes 7 cycles

c) read in cycle 4 is over by cycle 6, and write in cycle 4 is over by cycle 7, so it takes 8 cycles

2e

Even though this would sometimes be free computation (data copying) for an assembly language programmer, it probably requires some extra circuitry, and the main point is, since people don't write in assembly language directly much any more, the question is whether a compiler could ever output such an instruction. It's hard to see how it could. Perhaps it could recognize the specific swap idiom "t = x; x = y; y = t;", but even if so, this specific idiom doesn't occur frequently and even when it does occur it would be quite a coincidence if exactly one of x and y happened to be a register with the other being a memory location. So a compiler-writer is not going to attempt to recognize this situation. Thus, an EXCH instruction is simply not going to get used these days and it's not worth the extra circuitry.

Question 3

3. If Z bar then End
4. AddressFieldOfIR_out, PC_in, End

Question 4

4a

3. R1_out, Y_in
4. R0_out, Add, Z_in, Set CC
5. Z_out, R1_in, End

4b

3. R1_out, Y_in
4. R0_out, Add, ALU_out, R1_in, End, Set CC

Question 5

0. PC_out, Tie, MAR_in, Read
1. PC_out, Zero A, Set Carry-in, Add, ALU_out, PC_in, Wait MFC
2. MDR_out, Tie, IR_in

Question 6

       .ORG 42
       .WORD KBISR
       .WORD 200

       .ORG 1000  ; or wherever, but not amongst the interrupt vectors
KBISR: MOV R0, -(R6)
       MOV #3, R0
       CMP R0, 14  ; this performs a read of M[14], thus resetting the IRQ
       BNE NOPE
       MOV #2, R0
       JSR RAISE
 NOPE: MOV (R6)+, R0
       RTI

Question 7

One of the following must have been true:

R1 and R2 already had the same contents, and the microinstruction was R4_out, R3_in
R3 and R4 already had the same contents, and the microinstruction was R2_out, R1_in
R2 and R4 had the same contents, and the microinstruction was R2_out, R1_in, R3_in
R2 and R4 had the same contents, and the microinstruction was R4_out, R1_in, R3_in

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